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Direct Transistor Level Layout for Digital Blocks

Direct Transistor-Level Layout for Digital Blocks Publisher: Springer | Pages: 180 | 2004-06-17 | ISBN 1402076657 | PDF | 7 MB Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. [...]

Tags: Array, Cell Library, Density, Design Methodologies, Diffusion, Digital Circuits, Digital Logic, Digital Transistor, Flexibility, Layout Generation, Level Layout, Level Optimizations, Publisher Springer, Scales, Shape, Timing Optimization, Transistor Level, Transparent